PDF] A non-overlapping two-phase clock generator with adjustable duty cycle | Semantic Scholar
GitHub - jhpark16/FPGA-muti-clock-generator-275MHz-XC6SLX9: Multiple (8) high frequency clocks generated using a Xilinx XC6SLX9, VHDL and free Xilinx ISE.
Counter and Clock Divider - Digilent Reference
vhdl - Generating pulse train of varying frequency on an FPGA - Electrical Engineering Stack Exchange